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S5PV210數據手冊

軟件大小:84.6 M 軟件性質: 免費軟件
更新時間:2012/5/4 15:07:12 應用平臺:Win9X/Win2000/WinXP
下載次數:22604 下載來源:米爾科技
軟件語言:英文 軟件類別:開發板資料 > MYS-S5PV210 單板機
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》S5PV210開發板 》


S5PV210 is a 32-bit RISC cost-effective, low power, and high performance microprocessor solution for mobile phones and general applications. It integrates the ARM Cortex-A8 core, which implements the ARM architecture V7-A with supporting peripherals. To provide optimized Hardware (H/W) performance for the 3G and 3.5G communication services, S5PV210 adopts 64-bit internal bus architecture. This includes many powerful hardware accelerators for tasks such as motion video processing, display control, and scaling. Integrated Multi Format Codec (MFC) supports encoding and decoding of MPEG-1/2/4, H.263, and H.264, and decoding of VC1. This hardware accelerator (MFC) supports real-time video conferencing and Analog TV out, HDMI for NTSC, and PAL mode. S5PV210 has an interface to external memory that is capable of sustaining heavy memory bandwidths required in high-end communication services. The memory system has Flash/ ROM external memory ports for parallel access and DRAM port to meet high bandwidths. DRAM controller supports LPDDR1 (mobile DDR), DDR2, or LPDDR2. Flash/ ROM port supports NAND Flash, NOR-Flash, OneNAND, SRAM, and ROM type external memory. To reduce the total system cost and enhance the overall functionality, S5PV210 includes many hardware peripherals such as TFT 24-bit true color LCD controller, Camera Interface, MIPI DSI, CSI-2, System Manager for power management, ATA interface, four UARTs, 24-channel DMA, five Timers, General I/O Ports, three I2S, S/PDIF, three (general purpose) IIC-BUS interfaces, two HS-SPI, USB Host 2.0, USB 2.0 OTG operating at high speed (480Mbps), four SD Host and high-speed Multimedia Card Interface, and four PLLs for clock generation. Package on Package (POP) option with MCP is available for small form factor applications.

開發板資料

ARM開發工具

ARM工具手冊

資料下載

軟件例程

演示視頻

HMI資料

充電樁資料

工控板資料

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